FPL Implementation of a SIMD RISC RNS-Enabled DSP

VHDL synthesis and FPL implementation of a RNS-enabled RISC DSP are presented in this paper. Four parallel modular arithmetic units optimized for multiply-and-accumulate are used in a parallel SIMD architecture. The moduli 256, 251, 241 and 239 are selected to optimize area and performance. Thus, pipelined Galois Field multipliers are used for prime moduli while conventional adders and multipliers are used for power of two modulus. A three-level pipelined control unit prefetches, decodes and executes instructions over parallel high performance modular arithmetic enhanced channels. Performance and area were analysed through synthesis and simulation over Altera FLEX10K FPL devices. A representative set of DSP applications shows a sustained increase in performance when compared with commercially available and commonly used VLSI DSP technology. Key-Words: Residue Number System, SIMD-RISC Processor, DSP, Field Programmable Logic.